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Operational Phases and Modes of Operation
4.4
Clock operation as a function of mode/phase
Figure 4-6 illustrates the nominal phases of operation for this device. The values of ? A , ? D and ? I were
discussed briefly in “Frame structure” on page 35 . The reset operation is described in “Reset generation”
on page 191 . The sleep phase is defined as the device oscillator being off and all circuitry in its lowest
power state.
“Power control modes of operation” on page 42 maps these phases into modes of operation of the Version
1 Coldfire CPU.
There is a strong software component to the application phases diagrammed here. They may be rearranged
from time to time depending on the tasks assigned to the sensor. Tasks scheduling will be handled by the
Scheduler Application (ID 0x01) as described in the MMA955xL Intelligent, Motion-Sensing Platform
Software Reference Manual (MMA955XLSWRM).
RESET
? A
wri
t
eO
SC
T
RL
Software
Overrun
Condition
Special ? D
Boot Process
? D
Wake on external interrupt or
slave I 2 C command received.
SLEEP
CPU initiates
? I
Processor executes STOP
prior to “start data frame.”
Each pass through ? A to ? D and
to ? I constitutes one sample
frame. An output data frame is one
or more sample frames in length,
depending on the amount of over-
sampling being done.
Sleep mode.
Figure 4-6. Operational phases
The phases shown above have distinct characteristics with regard to clock operation. These are outlined in
Table 4-1 . The operation of clock-gating registers (PCERUNx, PCESSCx and PCESFCx) in the SIM do
not change as a result of debug operation, only the oscillator operation.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
40
Freescale Semiconductor, Inc.
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